Method, system and device for non-volatile memory device operation

ABSTRACT

Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No. ______ (TBD, Attorney Docket No. 252.P012), titled “MEMORY WRITE DRIVER, METHOD AND SYSTEM,” filed on Aug. 13, 2015, and incorporated herein by reference in its entirety.

BACKGROUND

1. Field

Disclosed are techniques for utilizing memory devices.

2. Information:

Non-volatile memories are a class of memory in which the memory cell or element does not lose its state after power supplied to the device is removed. The earliest computer memories, made with rings of ferrite that could be magnetized in two directions, were non-volatile, for example. As semiconductor technology evolved into higher levels of miniaturization, the ferrite devices were abandoned for the more commonly known volatile memories, such as DRAMs (Dynamic Random Access Memories) and SRAMs (Static-RAMs).

One type of non-volatile memory, electrically erasable programmable read-only memory (EEPROM) devices have large cell areas and may require a large voltage (e.g., from 12.0 to 21.0 volts) on a transistor gate to write or erase. Also, an erase or write time is typically of the order of tens of microseconds. One limiting factor with EEPROMs is the limited number of erase/write cycles to no more than slightly over 600,000—or of the order of 10⁵-10⁶. The semiconductor industry has eliminated a need of a pass-gate switch transistor between EEPROMs and non-volatile transistors by sectorizing a memory array in such a way that “pages” (e.g., sub-arrays) may be erased at a time in EEPROMs called flash memory devices. In flash memory devices, an ability to keep random access (erase/write single bits) was sacrificed for speed and higher bit density.

More recently, FeRAMs (Ferroelectric RAMs) have provided low power, relatively high write/read speed, and endurance for read/write cycles exceeding 10 billion times. Similarly, magnetic memories (MRAMs) have provided high write/read speed and endurance, but with a high cost premium and higher power consumption. Neither of these technologies reaches the density of flash memory devices, for example. As such, flash remains a non-volatile memory of choice. Nevertheless, it is generally recognized that flash memory technology may not scale easily below 65 nanometers (nm); thus, new non-volatile memory devices capable of being scaled to smaller sizes are actively being sought.

Technologies considered for the replacement of flash memory devices have included memories based on certain materials that exhibit a resistance change associated with a change of phase of the material (determined, at least in part, by a long range ordering of atoms in the crystalline structure). In one type of variable resistance memory called a phase change memory (PCM/PCRAM) devices, a change in resistance occurs as the memory element is melted briefly and then cooled to either a conductive crystalline state or a non-conductive amorphous state. Typical materials vary and may include GeSbTe, where Sb and Te can be exchanged with other elements of the same or similar properties on the Periodic Table. However, these resistance-based memories have not proved to be commercially useful because their transition between the conductive and the insulating state depends on a physical structure phenomenon (e.g., melting at up to 600 degrees C.) and returning to a solid state that cannot be sufficiently controlled for a useful memory in many applications.

Another variable resistance memory category includes materials that respond to an initial high “forming” voltage and current to activate a variable resistance function. These materials may include, for example, Pr_(x)Ca_(y)Mn_(z)O_(ε), with x, y, z and ε of varying stoichiometry; transition metal oxides, such as CuO, CoO, VO_(x), NiO, TiO₂, Ta₂O₅; and some perovskites, such as Cr; SrTiO₃. Several of these memory types exist and fall into the resistive RAMs (ReRAMs) or conductive bridge RAMS (CBRAM) classification, to distinguish them from the chalcogenide type memories. It is postulated that resistance switching in these RAMs is due, at least in part, to the formation of narrow conducting paths or filaments connecting the top and bottom conductive terminals by the electroforming process, though the presence of such conducting filaments are still a matter of controversy. Since operation of a ReRAM/CBRAM may be strongly temperature dependent, a resistive switching mechanism in a ReRAM/CBRAM may also be highly temperature dependent. Additionally, these systems may operate stochastically as the formation and movement of the filament is stochastic. Other types of ReRAM/CBRAM may also exhibit unstable qualities. Further, resistance switching in ReRAM/CBRAMs tends to fatigue over many memory cycles. That is, after a memory state is changed many times, a difference in resistance between a conducting state and an insulative state may change significantly. In a commercial memory device, such a change may take the memory out of specification and make it unusable.

Given an inherent difficulty in forming a thin film resistance switching material that is stable over time and temperature, a workable resistance switching memory remains a challenge. Furthermore, all resistance switching mechanisms developed up to now have been inherently unsuitable for memories, due to high currents, electroforming, no measurable memory read or write windows over a reasonable range of temperatures and voltages, and many other problems such as stochastic behavior. Thus, there remains a need in the art for a non-volatile memory that is deterministic has low power, high speed, high density and stability, and in particular, such a memory that is scalable to feature sizes well below 65 nanometers (nm).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a plot of current density versus voltage for a CES device according to an embodiment.

FIG. 1B is a schematic diagram of an equivalent circuit to a CES device according to an embodiment.

FIG. 2 is a schematic diagram of a memory circuit according to an embodiment.

FIGS. 3A, 3B and 3C are schematic diagrams of alternative implementations of a sense circuit according to particular embodiments

FIGS. 4A, 4B and 4C are schematic diagrams of alternative implementations of a write circuit according to particular embodiments.

FIGS. 5A through 5M are schematic diagrams of alternative architectures for a bitcell according to particular embodiments.

FIGS. 6A and 6B are timing diagrams for alternative architectures for a bitcell according to particular embodiments.

FIGS. 7A through 7E are schematic diagrams of alternative architectures for a bitcell according to particular embodiments.

FIGS. 8A through 8G are schematic diagrams of alternative architectures for a bitcell according to particular embodiments.

DETAILED DESCRIPTION

Particular aspects of the present disclosure incorporate a Correlated Electron Material (CEM) to form a correlated electron switch (CES). In this context, a CES may exhibit an abrupt conductor/insulator transition arising from electron correlations rather than solid state structural phase changes (e.g., crystalline/amorphous in phase change memory (PCM) devices or filamentary formation and conduction in resistive RAM devices as discussed above). In one aspect, an abrupt conductor/insulator transition in a CES may be responsive to a quantum mechanical phenomenon, in contrast to melting/solidification or filament formation. Such a quantum mechanical transition between conductive and insulative states in a CEM memory device may be understood in any one of several aspects.

In one aspect, a quantum mechanical transition of a CES between an insulative state and a conductive state may be understood in terms of a Mott transition. In a Mott transition, a material may switch from an insulative state to conductive state if a Mott transition condition occurs. The criteria may be defined by the condition (n_(C))^(1/3) a=0.26), where n_(C) is a concentration of electrons and “a” is a Bohr radius. If a critical carrier concentration is achieved such that the Mott criteria is met, a Mott transition may occur and state may change from a high resistance/capacitance to a low resistance/capacitance.

In one aspect, a Mott transition may be controlled by a localization of electrons. As carriers are localized, a strong coulomb interaction between electrons splits the bands of the material creating an insulator. If electrons are no longer localized, a weak coulomb interaction may dominate band splitting, leaving behind a metal (conductive) band. This is sometimes explained as a “crowded elevator” phenomenon. While an elevator has only a few people in it, the people can move around easily, which is analogous to a conducting state. While the elevator reaches a certain concentration of people, on the other hand, passengers can no longer move, which is analogous to the insulative state. However, it should be understood that this classical explanation provided for illustrative purposes, like all classical explanations of quantum phenomenon, is only an incomplete analogy, and that claimed subject matter is not limited in this respect.

In particular implementations of aspects of this disclosure, a resistive switching integrated circuit memory may comprise: a resistive switching memory cell including a CES device; a write circuit for placing the resistive switching memory cell in a first resistive state or a second resistive state depending on signals provided to the memory cell, wherein a resistance of the CES is higher in the second resistance state than in the first resistance state; and a read circuit for sensing the state of the memory cell and providing an electrical signal corresponding to the sensed state of the memory cell. In one aspect, a resistance of a CES in the second memory cell state may be more than 100 times the resistance in the second memory cell state. In a particular implementation, a CES device may switch resistive states responsive to a Mott-transition in the majority of the volume of the CES device. In one aspect, a CES device may comprise a material selected from a group comprising aluminum, cadmium, chromium, cobalt, copper, gold, iron, manganese, mercury, molybdenum, nickel, palladium, rhenium, ruthenium, silver, tin, titanium, vanadium, and zinc (which may be linked to a cation such as oxygen or other types of ligands), or combinations thereof.

In a particular embodiment, a CES device may be formed as a “CEM random access memory (CeRAM)” device. In this context, a CeRAM device comprises a material that may transition between or among a plurality of predetermined detectable memory states based, at least in part, on a transition of at least a portion of the material between a conductive state and an insulative state utilizing the quantum mechanical Mott transition. In this context, a “memory state” means a detectable state of a memory device that is indicative of a value, symbol, parameter or condition, just to provide a few examples. In one particular implementation, as described below, a memory state of a memory device may be detected based, at least in part, on a signal detected on terminals of the memory device in a read operation. In another particular implementation, as described below, a memory device may be placed in a particular memory state to represent or store a particular value, symbol or parameter by application of one or more signals across terminals of the memory device in a “write operation.”

In a particular implementation, a CES element may comprise material sandwiched between conductive terminals. By applying a specific voltage and current between the terminals, the material may transition between the aforementioned conductive and insulative memory states. As discussed in the particular example implementations below, material of a CES element sandwiched between conductive terminals may be placed in an insulative or high impedance memory state by application of a first programming signal across the terminals having a voltage V_(reset) and current I_(reset), or placed in a conductive or low impedance memory state by application of a second programming signal across the terminals having a voltage V_(set) and current I_(set). In this context, it should be understood that terms such as “conductive or low impedance” memory state and “insulative or high impedance” memory state are relative terms and not specific to any particular quantity or value for impedance or conductance. For example, while a memory device is in a first memory state referred to as an insulative or high impedance memory state the memory device in one aspect is less conductive (or more insulative) than while the memory device in a second memory state referred to as a conductive or low impedance memory state.

In a particular implementation, CeRAM memory cells may comprise a metal/CEM/metal (M/CEM/M) stack formed on a semiconductor. Such an M/CEM/M stack may be formed on a diode, for example. In an example, implementation, such a diode may be selected from the group consisting of a junction diode and a Schottky diode. In this context, it should be understood that “metal” means a conductor, that is, any material that acts like a metal, including, for example, polysilicon or a doped semiconductor.

FIG. 1A shows a plot of current density versus voltage across terminals (not shown) for a CES device according to an embodiment. Based, at least in part, on a voltage applied to terminals of the CES device (e.g., in a write operation), the CES may be placed in a conductive state or an insulative state. For example application of a voltage V_(set) and current density J_(set) may place the CES device in a conductive memory state and application of a voltage V_(reset) and a current density J_(reset) may place the CES device in an insulative memory state. Following placement of the CES in an insulative state or conductive state, the particular state of the CES device may be detected by application of a voltage V_(read) (e.g., in a read operation) and detection of a current or current density at terminals of the CeRAM device.

According to an embodiment, the CES device of FIG. 1A may include any TMO, such as, for example, perovskites, Mott insulators, charge exchange insulators, and Anderson disorder insulators. In particular implementations, a CES device may be formed from switching materials such as nickel oxide, cobalt oxide, iron oxide, yttrium oxide, and perovskites such as Cr doped strontium titanate, lanthanum titanate, and the manganate family including praesydium calcium manganate, and praesydium lanthanum manganite, just to provide a few examples. In particular, oxides incorporating elements with incomplete d and f orbital shells may exhibit sufficient resistive switching properties for use in a CES device. In an embodiment, a CES device may be prepared without electroforming. Other implementations may employ other transition metal compounds without deviating from claimed subject matter. For example, {M(chxn)₂Br}Br₂ where M may comprise Pt, Pd, or Ni, and chxn comprises 1R,2R-cyclohexanediamine, and other such metal complexes may be used without deviating from claimed subject matter.

In one aspect, the CES device of FIG. 1A may comprise materials that are TMO metal oxide variable resistance materials, though it should be understood that these are exemplary only, and are not intended to limit claimed subject matter. Particular implementations may employ other variable resistance materials as well. Nickel oxide, NiO, is disclosed as one particular TMO. NiO materials discussed herein may be doped with extrinsic ligands, which may stabilize variable resistance properties. In particular, NiO variable resistance materials disclosed herein may include a carbon containing ligand, which may be indicated by NiO(C_(x)). Here, one skilled in the art may determine a value of x for any specific carbon containing ligand and any specific combination of carbon containing ligand with NiO simply by balancing valences. In another particular example, NiO doped with extrinsic ligands may be expressed as NiO(L_(x)), where L_(x) is a ligand element or compound and x indicates a number of units of the ligand for one unit of NiO. One skilled in the art may determine a value of x for any specific ligand and any specific combination of ligand with NiO or any other transition metal simply by balancing valences.

If sufficient bias is applied (e.g., exceeding a band-splitting potential) and the aforementioned Mott condition is met (injected electron holes=the electrons in a switching region), the CES device may rapidly switch from a conductive state to an insulator state via the Mott transition. This may occur at point 108 of the plot in FIG. 1A. At this point, electrons are no longer screened and become localized. This correlation may result in a strong electron-electron interaction potential which splits the bands to form an insulator. While the CES device is still in the insulative state, current may generated by transportation of electron holes. If enough bias is applied across terminals of the CES, electrons may be injected into a metal-insulator-metal (MIM) diode over the potential barrier of the MIM device. If enough electrons have been injected and enough potential is applied across terminals to place the CES device in a set state, an increase in electrons may screen electrons and remove a localization of electrons, which may collapse the band-splitting potential forming a metal.

According to an embodiment, current in a CES device may be controlled by an externally applied “compliance” condition determined based, at least in part, on the external current limited during a write operation a write operation to place the CES device in an insulative state. This externally applied compliance current may also set a condition of a current density for a subsequent reset operation to place the CES in a conductive state. As shown in the particular implementation of FIG. 1A, a current density J_(comp) applied during a write operation at point 116 to place the CES device in an insulative state may determine a compliance condition for placing the CES device in a conductive state in a subsequent write operation. As shown, the CES device may be subsequently placed in a conductive state by application of a current density J_(reset)≧J_(comp) at a voltage V_(reset) at point 108, where J_(comp) is externally applied.

The compliance therefore may set a number of electrons in a CES device which are to be “captured” by holes for the Mott transition. In other words, a current applied in a write operation to place a CES device in a conductive memory state may determine a number of holes to be injected to the CES device for subsequently transitioning the CES device to an insulative memory state.

As pointed out above, a reset condition may occur in response to a Mott transition at point 108. As pointed out above, such a Mott transition may occur at condition in a CES device in which a concentration of electrons n equals a concentration of electron holes p. This condition may be modeled according to expression (1) as follows:

$\begin{matrix} {{{\lambda_{TF}n^{\frac{1}{3}}} = {\left. C \right.\sim 0.26}}{n = \left( \frac{C}{\lambda_{TF}} \right)^{3}}} & (1) \end{matrix}$

where:

-   -   λ_(TF) is a Thomas Fermi screening length; and     -   C is a constant.

According to an embodiment, a current or current density in a region 104 of the plot shown in FIG. 1A may exist in response to injection of holes from a voltage signal applied across terminals of a CES device. Here, injection of holes may meet a Mott transition criterion for the conductive state to insulative state transition at current I_(MI) as a critical voltage V_(MI) is applied across terminals of CES device. This may be modeled according to expression (3) as follows:

$\begin{matrix} {{{I_{MI}\left( V_{MI} \right)} = {\frac{{Q\left( V_{MI} \right)}}{t} \approx \frac{Q\left( V_{MI} \right)}{t}}}{{Q\left( V_{MI} \right)} = {{qn}\left( V_{MI} \right)}}} & (3) \end{matrix}$

-   -   Where Q(V_(MI)) is the charged injected (hole or electron) and         is a function of an applied voltage.         Injection of electron holes to enable a Mott transition may         occur between bands and in response to critical voltage V_(MI).         and critical current I_(MI). By equating electron concentration         n with a charge concentration to bring about a Mott transition         by holes injected by I_(MI) in expression (3) according to         expression (1), a dependency of such a critical voltage V_(MI)         on Thomas Fermi screening length λ_(TF) may be modeled according         to expression (4) as follows:

$\begin{matrix} {{{I_{MI}\left( V_{MI} \right)} = {\frac{Q\left( V_{MI} \right)}{t} = {\frac{{qn}\left( V_{MI} \right)}{t} = {\frac{q}{t}\left( \frac{C}{\lambda_{TF}} \right)^{3}}}}}{{J_{reset}\left( V_{MI} \right)} = {{J_{MI}\left( V_{MI} \right)} = {\frac{I_{MI}\left( V_{MI} \right)}{A_{CeRam}} = {\frac{q}{A_{CeRam}t}\left( \frac{C}{\lambda_{TF}\left( V_{MI} \right)} \right)^{3}}}}}} & (4) \end{matrix}$

Where:

-   -   A_(CeRam) is a cross-sectional area of a CES element; and     -   J_(reset)(V_(MI)) is a current density through the CES element         to be applied to the CES element at a critical voltage V_(MI) to         place the CES element in an insulative state.

According to an embodiment, a CES element may be placed in a conductive memory state (e.g., by transitioning from an insulative memory state) by injection of a sufficient number of electrons to satisfy a Mott transition criteria.

In transitioning a CES to a conductive memory state, as enough electrons have been injected and the potential across terminal of the CES device overcomes a critical switching potential (e.g., V_(set)), injected electrons begin to screen and unlocalize double-occupied electrons to reverse a disproportion reaction and closing the bandgap. A current density J_(set)(V_(MI)) for transitioning the CES to the conductive memory state at a critical voltage V_(MI) enabling transition to the conductive memory state may be expressed according to expression (6) as follows:

$\begin{matrix} {{{I_{IM}\left( V_{IM} \right)} = {\frac{{Q\left( V_{IM} \right)}}{t} \approx \frac{Q\left( V_{IM} \right)}{t}}}{{Q\left( V_{IM} \right)} = {{qn}\left( V_{IM} \right)}}{{I_{IM}\left( V_{IM} \right)} = {\frac{Q\left( V_{IM} \right)}{t} = {\frac{{qn}\left( V_{IM} \right)}{t} = {\frac{q}{t}\left( \frac{C}{a_{B}} \right)^{3}}}}}{{J_{set}\left( V_{IM} \right)} = {{J_{injection}\left( V_{IM} \right)} = {{J_{IM}\left( V_{IM} \right)} = {\frac{I_{IM}\left( V_{IM} \right)}{A_{CeRam}} = {\frac{q}{A_{CeRam}t}\left( \frac{C}{a_{B}} \right)^{3}}}}}}} & (6) \end{matrix}$

where:

-   -   a_(B) is a Bohr radius.

According to an embodiment, a “read window” 102 for detecting a memory state of a CES device in a read operation may be set out as a difference between a portion 106 the plot of FIG. 1A while the CES device is in an insulative state and a portion 104 of the plot FIG. 1A while the CES device is in a conductive state at a read voltage V_(read). In a particular implementation, read window 102 may be used to determine a Thomas Fermi screening length λ_(TF) of material making up the CES device. For example, at a voltage V_(reset), current densities J_(reset) and J_(set) may be related to according to expression (7) as follows:

$\begin{matrix} {{\lambda_{TF}\left( {@V_{reset}} \right)} = {a_{B}\left( \frac{J_{reset}}{J_{off}} \right)}^{\frac{1}{3}}} & (7) \end{matrix}$

In another embodiment, a “write window” 110 for placing a CES device in an insulative or conductive memory state in a write operation may be set out as a difference between V_(reset) (at J_(reset)) and V_(set) (at J_(set)). Establishing |V_(set)|>|V_(reset)| enables a switch between conductive and insulative state. V_(reset) may be approximately at a band splitting potential arising from correlation and V_(set) may be approximately twice the band splitting potential. In particular implementations, a size of write window 110 may be determined, at least in part, by materials and doping of the CES device.

The transition from high resistance/capacitance to low resistance/capacitance in a CES device may be represented by a singular impedance of the CES device. FIG. 1B depicts a schematic diagram of an equivalent circuit of an example variable impeder device (such as a CES device), such as variable impeder device 124. As mentioned, variable impeder device 124 may comprise characteristics of both variable resistance and variable capacitance. For example, an equivalent circuit for a variable impeder device may, in an embodiment, comprise a variable resistor, such as variable resistor 126 in parallel with a variable capacitor, such as variable capacitor 128. Of course, although a variable resistor 126 and variable capacitor 128 are depicted in FIG. 1B as comprising discrete components, a variable impeder device, such as variable impeder device 124, may comprise a substantially homogenous CEM, wherein the CEM comprises characteristics of variable capacitance and variable resistance. Table 1 below depicts an example truth table for an example variable impeder device, such as variable impeder device 100.

TABLE 1 Resistance Capacitance Impedance R_(high) (V_(applied)) C_(high) (V_(applied)) Z_(high) (V_(applied)) R_(low) (V_(applied)) C_(low) (V_(applied))~0 Z_(low) (V_(applied))

FIG. 2 is a schematic diagram of a memory circuit according to an embodiment. A bitcell circuit 200 may comprise one or more memory elements (e.g., non-volatile memory elements) comprising a CES device. In this context, a “bitcell” or “bitcell circuit” as referred to herein comprises a circuit or portion of a circuit capable of representing a value, symbol or parameter as a state. For example, a bitcell may comprise one or more memory devices that capable of representing a value, symbol or parameter as a memory state of the memory device. In particular implementations, a bitcell may represent a value, symbol or parameter as a single bit or multiple bits.

According to an embodiment, bitcell circuit 200 may comprise memory elements having a behavior similar to that of the CES device discussed above in connection with FIG. 1 For example, a memory element in bitcell 200 may be placed in a particular memory state (e.g., a conductive or low impedance memory state, or insulative or high impedance memory state) by independently controlling voltage and current applied across terminals of the memory element in a “write operation.” As discussed below in particular implementations, such a write operation may be executed by application of a signal which is controlled to provide a critical current and voltage across terminals of the memory device to place the memory device in a particular memory state. In another aspect, a memory state of a memory element in bitcell 200 may be detected or sensed in a “read operation” by precharging a bitline BL by closing transistor M0 in response to a drop in voltage of signal PRN to connect bitline BL with voltage RVDD=0.4V. Transistor M0 may subsequently open in response to an increase in voltage of signal PRN, followed by a closing of transistor M3 in response to an increase in voltage of signal RD_Col_Sel to connect bitline BL to sense circuit 203. In this context, a “bitline” comprises a conductor that is connectable to at least one terminal of a memory element during a write operation to transmit a signal altering a memory state of the memory element, or during a read operation to transmit a signal indicative of a current memory state of the memory element. Sense circuit 203 may detect a memory state of the memory element in bitcell 200 based on a magnitude of current or voltage from bitline BL through transistor M3 in a read operation. An output signal may have a voltage that is indicative of a current memory state of bitcell 200 (e.g., as a “1,” “0” or other symbol). In one aspect of a read operation, to detect a current memory state of a memory element, a voltage of a signal applied across terminals of the memory element in bitcell 200 may be controlled so as to not detectably alter the current memory state of the memory element.

FIGS. 5A through 8G are directed to specific implementations of a bitcell circuit that include CES devices or elements to store a particular memory state. While the description below provides CeRAM devices or non-volatile memory elements as specific examples of devices in a bitcell capable of maintaining a memory state, it should be understood that these are merely example implementations. For example, it should be recognized a CES adapted for purposes other than a non-volatile memory device or CeRAM device may be used for storing a particular memory state (e.g., a conductive or low impedance memory state, or an insulative or high impedance memory state) in a write operation which is detectable in a subsequent read operation, and that claimed subject matter is not limited to either implementation of a CeRAM or non-volatile memory devices.

Particular example implementations of sense circuit 203 are shown in the schematic diagrams of FIGS. 3A through 3C. As shown in the particular example implementations, a sense circuit may comprise a single-ended sense amplifier circuit including a voltage mode amplifier as shown in FIG. 3A or a current mode amplifier as shown in FIG. 3C. The particular implementation of FIG. 3A comprises a differential voltage amplifier formed by field effect transistors (FETs) M7, M8, M9 and M10 to receive a signal from a bitline during a read operation and a reference voltage VREF. In a particular implementation, a signal maintained at a reference voltage VREF may be generated using a VREF circuit shown in the schematic diagram of FIG. 3B according to an embodiment. Here, reference voltage VREF may be set to VIN/2, where VIN is a voltage level on a bitline during a read operation. The VREF circuit of FIG. 3B may be activated during a read operation and generate a signal maintained at reference voltage VREF voltage using a resistor divider of two equal value hi-res Poly or Nwell resistors, R1 and R2, for example. It should be understood that this is merely an example of a circuit to generate a signal maintained at a reference voltage, and that claimed subject matter is not limited in this respect. For example, a differential voltage mode sense amplifier is for illustrative purposes only. A differential latch based voltage mode sense amplifier may also be used without deviating from claimed subject matter.

As pointed out above, another particular example implementation of a sense circuit is shown in the particular example implementation of a current mode sense amplifier shown in FIG. 3C. Here, a first stage comprises a current mirror which senses the voltage on the bitline, VIN at a gate terminal of transistor M12. A default state of the current sense mode amplifier of FIG. 3C is reading a value of “1” since the bitline is precharged to a particular voltage (e.g., 0.4V) while the sense circuit of FIG. 3C is in a standby state with a voltage at SAE=0.0 V at a beginning of a read cycle. If a bitcell is written to a “0” level, the bitline may be pulled from 0.4V to 0.0V which appears as VIN while at the same signal SAE may be pulled to voltage VDD. This may turn on transistor M12 to mirror a current into a second stage forcing node 7 to be pulled to 0.0 V while pulling the sense circuit output SAOUT is to voltage VDD. At the end of a read cycle, signal SAE may return to 0.0V and the sense circuit of FIG. 3C may return to a standby state. It should be understood that the above described implementations of a sense circuit as illustrated in FIGS. 3A through 3C are merely example implementations, and that claimed subject matter is not limited by these particular example implementations.

In another aspect, bitcell 200 may be changed to or placed in a particular memory state (e.g., set or reset) in a write operation by applying a voltage signal Wrt_Col_SelN to close transistor M4, connecting an adjustable driver circuit of write circuit 202 to bitline BL. In a particular implementation, write circuit 202 may drive a write supply voltage, WVDD, to a bitcell while a signal Wrt_Col_SelN is maintained at 0.0 V. As pointed out above, a memory state of a CES device may be placed in a set or reset memory by controlling a voltage and a current applied to terminals of the CES device. In a particular non-limiting example implementation, a signal generated by a write supply voltage WVDD may be driven to particular voltage levels to match the reset and set voltages V_(reset) and V_(set) for a CES device (e.g., 0.6V or 1.2V). In addition, write circuit 202 may comprise an adjustable strength driver to control a current density supplied to the CES device.

As pointed out above in FIG. 1, a memory state of a CES device in bitcell 200 may be changed or determined based on a particular voltage and current applied to bitline BL. For example, providing a signal to bitline BL having a voltage V_(reset) and a sufficient current I_(reset) may place a CES device of bitcell 200 in an insulative or high impedance memory state. Likewise, providing a signal to bitline BL having a voltage V_(set) and a sufficient current I_(set) may place a CES device of bitcell 200 in a conductive or low impedance memory state. As may be observed from FIG. 1, that while a magnitude of voltage V_(set) is greater than a magnitude of voltage V_(reset), a magnitude of current I_(set) is lower than a magnitude of current I_(reset).

FIGS. 4A and 4B are schematic diagrams of alternative implementations for write circuit 202 according to alternative implementations. In particular, a write operation is described as a particular process of placing a memory device such as a CES element in a particular memory state of a plurality of predetermined memory states by applying a “programming signal” to terminals of the memory device. Particular ones of the predetermined memory states may correspond to particular voltage levels to be applied to the memory device (e.g., V_(set) and V_(reset)). Similarly, particular ones of the predetermined memory states may correspond to particular current levels to be applied to the memory device (e.g., I_(set) and I_(reset)). Accordingly, in a particular embodiment, a programming signal to place a CES device in a particular memory state in a write operation may be controlled to have a particular voltage level and current level corresponding to the particular memory state. The specific example embodiments of FIGS. 4A and 4B are directed to providing a programming signal to a “single-ended” bitcell to place the particular bitcell in a particular memory state. It should be understood, however, that aspects of the specific example embodiments of FIGS. 4A and 4B may be applicable to generating one or more programming signals to place multiple CES elements in a bitcell to memory states based on a data signal, and that claimed subject matter is not limited to the specific example embodiments of FIGS. 4A and 4B. For example, a first write circuit according to FIG. 4A or 4B may be configured to apply a first programming signal placing a first CES element of a bitcell in a particular memory state and a second, replicated write circuit may be configured to apply a second programming placing a second CES element of the bitcell in a complementary memory state.

As described in a particular implementation below, a voltage signal having a voltage level for a programming signal to place a memory device in a predetermined memory state may be selected at a signal selection circuit based, at least in part, on a data signal. Conducting elements connected to the signal selection circuit may selectively connect the voltage signal to or disconnect the voltage signal from the memory device at a current level corresponding to the predetermined memory state based, at least in part, on the data signal. In this context, a “conducting element” comprises a circuit element capable of permitting current to pass between two nodes. In a particular implementation, a conducting element may vary a current permitted to pass between nodes based, at least in part, on a particular condition. The particular implementations described below employ FETs as conducting elements to permit current to pass between source and drain terminals based, at least in part, on a voltage applied to a gate terminal. It should be understood, however, that other types of devices such as, a bipolar transistor, diode, variable resistor, etc. may be used as a conducting element, and that claimed subject matter is not limited this respect. In this context, a conducting element having first and second terminals may “connect” the first and second terminals by providing a conductive path between the first and second terminals having a very small or negligible impedance for a particular signal. In one particular example implementation, a conductive element may vary an impedance between the first and second terminals based, at least in part, on a signal provided to a third terminal of the conductive element (e.g., a based on a voltage or current applied to the third terminal). In one aspect, a conductive element may “close” to thereby connect first and second terminals in response to a signal provided on the third terminal. Likewise, a conductive element may “open” to thereby disconnect first and second terminals in response to a different signal provide on the third terminal. In one aspect, a conductive element in an open state may isolate a first portion of a circuit from a second portion of the circuit by removing or disrupting a conductive path between the first and second portions of the circuit. In another aspect, a conducting element may vary an impedance between first and second terminals between opened and closed state based on a signal provided to a third terminal.

According to an embodiment, a signal may be provided to a bitline in an operation based, at least in part, on whether the operation is a read operation or a write operation. A signal WE may be received at an inverter 304 to provide a signal WEN to gates of FETs M34 and M30. If the particular operation is a read operation, transistor M34 may be closed in response to signal WE while FETs M30 and M32 may be opened in response to a voltage of signal WE to provide a voltage V_(read) to the bitline. Furthermore, connecting voltage V_(read) to FET M4 allows for less precise timing of closing M4 at the commencement of a write operation to apply a programming signal to a memory element. While FIGS. 4A, 4B and 4C show that FET M4 connects a single bitline BL to a write circuit, in particular implementations FET M4 may be among multiple conducting elements in a multiplexer to selectively connect an output signal of a write circuit to a bitline selected among multiple bitlines (e.g., where the write circuit is configured to provide a programming signal to any one of multiple bitlines leading to bitcells). In other embodiments in which one write circuit is provided per bitline, an output signal of a write circuit may be connected directly to a bitline without a connection from a conducting element responsive to a column select signal (e.g., without FET M4).

If the particular operation is a write operation, signal WEN may be at 0.0 V and FET M34 may be opened in response to a drop of a voltage on signal WEN to disconnect bitline BL from voltage V_(read). In response to a lowered voltage on signal WEN to connect bitline BL to a programming signal maintained at a particular voltage and current to place a bitcell in either a conductive or low impedance memory state, or an insulative or high impedance memory state. FET M32 may be closed in a write operation to place the memory element in an insulative or high impedance memory state (e.g., for writing a “0”) in a reset operation. For example, as shown in FIG. 4A, this may occur as signal WEN is low while Data=“0” to close FET M32 as a voltage expressed by the condition “WEN or Data” is applied to a gate terminal of FET M32.

According to an embodiment, a multiplexer 302 may receive a voltage signal having a voltage V_(set) and a voltage signal having a voltage V_(reset) (e.g., critical voltages for placing a CES device in a conductive or low impedance memory state, or an insulative or high impedance memory state). According to an embodiment, voltage signals having voltages V_(set) and V_(reset) may be generated using any one of several circuits (not shown) including amplifiers and the like for generating a signal having a controlled voltage and/or current. Multiplexer 302 may select between providing a signal at voltage V_(set) or voltage V_(reset) to FETs M30 and M32 based, at least in part, on a data signal having a value of “1” or “0.” In an embodiment, FET M30 may close in response to a lowered voltage on signal WEN to connect a selected voltage signal to bitline BL. Depending on whether the data signal has a value of “1” or “0,” a magnitude of current provided to bitline BL may be affected. As illustrated above with reference to FIG. 1, a write operation to modify a memory state of a CES device to an insulative or high impedance memory state may be accomplished with a higher current density J_(reset) than a current density J_(set) to modify the memory state to a conductive or low impedance memory state. In a particular implementation, FET M32 and FET M30 may connect V_(reset) to the bitline based on the value of the data signal received at multiplexer 302. As such, if a data signal received at multiplexer 302 in a write operation is a “0” for placing a CeRAM device in an insulative or high impedance memory state, both FETs M30 and M32 may be closed to permit sufficient current to flow to bitline BL at voltage V_(reset) for placing the CeRAM device in an insulative or high impedance memory state. On the other hand, if a data signal received at multiplexer 302 in a write operation is a “1” for placing a CeRAM device in a conductive or low impedance memory state, FET M30 may be closed in response to a raised voltage of signal WE while FET M32 remains open to limit current flowing to bitline BL at voltage V_(set) for placing the CeRAM device in a conductive or low impedance memory state.

In the alternative implementation of FIG. 4B, multiplexer 352 may select between providing V_(set) or V_(reset) to FETs M38 and M40 in a write operation based, at least in part, on a data signal having a value of “1” or “0.” In a read operation, a voltage of signal WE may be lowered such that transistor M36 is closed to connect a voltage V_(read-ref) to bitline BL, and such that FETs M38 and M40 are opened to disconnect multiplexer 352 from bitline BL. In a write operation, a voltage of signal WE may be raised such that FET M36 is opened to disconnect voltage V_(read-ref) from bitline BL, and such that FET M38 is closed to connect a signal selected at multiplexer 352 to bitline BL through at least FET M38. If a data signal received at multiplexer 352 in a write operation is a “0” for placing a CeRAM element in an insulative or high impedance memory state, both FETs M38 and M40 may be closed to permit sufficient current to flow to bitline BL at voltage V_(reset) to place the CeRAM element in an insulative or high impedance memory state. On the other hand, if a data signal received at multiplexer 352 in a write operation is a “1” for placing a CeRAM element in a conductive or low impedance memory state, transistor M38 may be closed while transistor M40 remains open to limit current flowing to bitline BL at voltage V_(set) to place the CeRAM element in a conductive or low impedance memory state.

The particular example implementations of FIGS. 4A and 4B are capable of providing a read voltage signal to bitline BL during read operations. Here, signal Wrt_Col_SelN may be lowered during read operations to close FET M4 and connect the read voltage signal to bitline BL (in addition to being lowered during write operations to connect a programming signal to bitline BL). In alternative implementations (as described below), a read voltage may be generated locally at bitcell 200 to be provided to terminals of a memory element during read operations. In which case, signal Wrt_Col_SelN may be raised during read operations to open FET M4 signal and disconnect write circuit from bitline BL.

The particular example embodiments of FIGS. 4A and 4B above multiplexers 302 and 352 provide examples of a “signal selection circuit.” In this context, a signal selection circuit provides circuit for selection of a signal having a particular voltage and current to be applied to a device. It should be understood, that multiplexers 302 and 352 are merely examples of a signal selection circuit, and that claimed subject matter is not limited in this respect. For example, a signal selection circuit may comprise select a signal generated from a source external to the signal selection circuit or generate a selected signal internally. In the particular write circuit of FIG. 4C, for example, a value of Data as “0” may close FET M44 and open FET M46 to provide a signal having a current I_(reset). FETs M48, M52 and M54 may also close to provide a lower voltage. A value of Data as “1,” on the other hand, may open FET M44 and close FET M46 to provide a signal having a current I_(set). FETs M48, M52 and M54 may also open to provide a higher voltage.

FIGS. 5A and 5B are schematic diagrams of alternative architectures for a bitcell according to particular embodiments. In a particular implementation of a read operation, a bitline may be connected to a first terminal of a first terminal of a non-volatile memory (NVM) element in a read operation through a first conducting element in response to a voltage signal on a wordline while the NVM is connected between a read supply voltage and a reference node. As pointed out above, a “non-volatile memory” comprises an integrated circuit device in which a memory cell or element maintains its memory state (e.g., conductive or low impedance memory state, or an insulative or high impedance memory state) after power supplied to the device is removed. In this context, a “wordline” comprises a conductor for transmitting a signal to select a particular bitcell or group of bitcells to be accessed in a read operation or a write operation. In a particular example implementation, a voltage of a signal on a wordline may be raised or lowered to select or deselect a particular bitcell or group of bitcells to be connected to a corresponding bitline or group of bitlines during a read or write operation. It should be understood, however, that this is merely an example of a wordline and that claimed subject matter is not limited in this respect. Also, in this context, a “reference node” comprises a node in a circuit that is maintained at a particular voltage level or at a particular voltage difference from another node in the circuit. In one example, a reference node may comprise or be connected to a ground node. In other particular implementations, a reference node may be maintained at a particular voltage relative to that of a ground node.

Subsequent to the read operation, in a first write operation to place the NVM in a first memory state, the bitline may be connected again to the first terminal to the NVM element through the first conducting element in response to the voltage signal on the wordline while isolating the NVM element from the read supply voltage or the reference node. In the first write operation, a programming signal having a first write voltage and a first write current may be applied across terminals of the NVM element to place the NVM element in a first memory state (e.g., an insulative or high impedance memory state). In a second write operation to place the NVM element in a second memory state, the bitline may be connected again to the first terminal of the NVM element through the first conducting element in response to the voltage signal on the wordline while isolating the NVM element from the read supply voltage or the reference node. The second write operation may apply a programming signal having a second write voltage and a second write current between terminals of the NVM element to place the NVM element in a second memory state (e.g., a conductive or low impedance memory state). In a particular implementation, the NVM element may comprise a CES element having one or more properties discussed above with reference to FIG. 1 in that |V_(reset)|<|V_(set)| while |I_(reset)|>|I_(set)|. Accordingly, in the particular examples illustrated in FIGS. 5A and 5B, a magnitude of the first write voltage may be greater than a magnitude of the second write voltage, and a magnitude of the first write current may be less than a magnitude of the second write current.

In FIG. 5A, NVM element 52 may comprise a CeRAM memory element connected to and a reference node 56 at a second terminal. In a particular implementation, such reference node 56 may be connected to a ground node. In another particular implementation, reference node 56 may be maintained at a particular reference voltage level (e.g., at a voltage relative to a ground node). In a read operation, a FET M2 may provide a conducting element to close in response to a lowered voltage of signal REN, connecting a read voltage to the first terminal of NVM element 52. In a write operation, FET M2 may open in response to a raised voltage on signal REN to disconnect the read voltage from the first terminal. An FET M1 may provide a conducting element to connect the first terminal of NVM 52 to a bitline BL during a read or a write operation during in response to a raised voltage on a wordline signal WL applied to a gate terminal of FET M1.

As pointed out above, a write circuit may independently control a voltage and a current of a signal applied to NVM element 52 in a write operation based, at least in part, on whether the write operation is to place NVM element 52 in a conductive or low impedance memory state, or an insulative or high impedance state. For example, for a write operation to place NVM element 52 in a conductive or low impedance memory state, a signal having a voltage V_(set) and a current I_(set) may be applied. Likewise, for a write operation to place NVM element 52 in an insulative or high impedance memory state, a signal having a voltage V_(reset) and a current I_(reset) may be applied. As illustrated in FIG. 1, voltage V_(set) may have a greater magnitude than voltage V_(reset) while current I_(set) may have a smaller magnitude than current I_(reset). As discussed above in a particular implementation, write circuit 202 may independently control voltage and current to provide a signal to a bitline to place a non-volatile memory device in a conductive or low impedance memory state, or an insulative or high impedance state. In a particular implementation, a voltage on a wordline may be “boosted” in a write operation to place NVM element 52 in an insulative or high impedance memory state to permit an increased current (I_(reset)) to flow between nodes 1 and 2.

As shown in FIGS. 5A and 5B, FET M2 may be implemented as either a PFET or NFET. A read analog supply voltage RVDD may be chosen to be 0.4V for a CeRAM read operation and low power. Read analog supply voltage RVDD may also be used for a bitline precharge circuit. Limiting a voltage swing of signal REN to between 0.0 and 0.4V to open or close FET M2 may enable relatively low power consumption. Alternatively, for slightly more power, but smaller area, FETs M1 and M2 may be formed in the same well. Additionally, a stack between FET M2 (or FET M1) and NVM element 52 may be reversed such that NVM element 52 is between read voltage supply RVDD and node 2, and a FET (e.g., FET M2 or FET M1) may be formed between node 2 and V_(ss). In a particular implementation write path voltages may be changed in order to generate critical voltages V_(set) and V_(reset) for placing NVM element 52 in a conductive or low impedance memory state, or an insultive or high impedance memory state.

It should be understood that the particular implementations discussed above with reference to FIGS. 5A and 5B are merely non-limiting examples, and that other particular implementations may be used without deviating from claimed subject matter. For example, in the particular alternative implementation of FIG. 5C, NVM 52 is positioned in the pull-up location connected directly to voltage source RVDD at a first terminal and connected to FET M2 at a second terminal. FET M2 may then be connected to reference node 56 to then connect NVM 52 to reference node 56 in response to a raised voltage on signal RE during a read operation. In the particular alternative example shown in FIG. 5D, FET M1 comprises a PFET to connect NVM 52 to bitline BL during read and write operations in response to a lowered voltage on wordline signal WLB. By implementing FET M1 as a PFET, FET M1 may permit an increased current between nodes 1 and 2 during write operations (e.g., to enable a current I_(reset) sufficient to place a memory state of NVM 52 in an insulative or high impedance memory state).

In the particular implementation of FIG. 5E, FET M1 is replaced with a transmission gate T3 comprising an NFET and a PFET to connect nodes 1 and 2 responsive to a raised voltage on wordline signal WL and a lowered voltage on wordline signal WLB during read or write operations. Here, in a closed state the NFET portion of transmission gate T3 may enable small currents to pass between nodes 1 and 2 during read operations while the PFET portion of transmission gate T3 may permits larger currents to pass between nodes 1 and 2 during write operations. It should be understood that the particular implementations of FIGS. 5A through 5E are merely example implementations and that claimed subject matter is not limited in these respects. For example, different features may be provided in specific implementations as shown in FIGS. 5F through 5M.

Table 2 below summarizes various signal voltages occurring during read and write operations in connection with the bitcell circuit of FIG. 5A (as integrated as a particular implementation of bitcell 200 of FIG. 1, for example) according to a particular implementation. Write supply voltage WVDD and write enable WEN may be applied to an adjustable driver of write circuit 202. A lowered voltage on signal PRN may close FET M0 during read or write operations to precharge bitline BL. A lowered voltage on signal Wrt_Col_SelN may close FET M4 during write operations to connect write circuit 202 to bitline BL, and a raised voltage on signal Wrt_Col_SelN may open FET M4 to disconnect write circuit 202 from bitline BL during read operations. Similarly, a raised voltage on signal RD_Col_Sel may close FET M3 during a read operation to connect sense circuit 203 to bitline BL, and a lowered voltage on open FET M3 during a write operation to disconnect sense circuit 203 from bitline BL. It should be clear to those of ordinary skill that similar signal voltages may be applied during read and write operations in connection with the bitcell circuits of FIGS. 5B through 5E. For example, in the particular bitcell circuit example of FIG. 5B, read enable signal REN may be active high during a read operation (e.g., at VDD).

TABLE 2 Mode RVDD WVDD WEN REN BL PRN SAE WL Wrt_Col_SellN RD_Col_Sel Read 0.4 VDD VDD 0  0-0.4 0-0.4 VDD VDD VDD VDD Write 0.4 0.6-1.2 0 0.4 0.6-1.2 0.4 0 VDD + VT + Margin 0 0

FIG. 6A is a timing diagram illustrating events during a read operation according to an embodiment of the bitcell shown in FIG. 5A. Also, FIG. 6B is a timing diagram illustrating events during a write operation according to an embodiment of a bitcell shown in FIG. 5A.

In FIGS. 5A and 5B, in a particular implementation where NVM element 52 comprises a CES element, as discussed above in connection with FIG. 1B NVM element 52 may have properties of a resistor and a capacitor coupled in parallel. In a particular implementation where NVM element 52 comprises a CES element, it should be understood that NVM element 52 comprises a single substantially homogenous CEM between terminals having a variable resistance and variable capacitance determined based, at least in part, on a particular memory state of NVM element 52. As such, it should be understood from FIG. 1B and the related discussion above that there are no separately formed resistor and capacitor as separate or discrete elements.

According to an embodiment, a capacitance of NVM 52 and a resistance of NVM 52 may vary depending on a particular memory state of NVM element 52. For example, the capacitance of and resistance of NVM 52 may be high as NVM element 52 is in an insulative or high impedance memory state. Likewise, the capacitance and resistance of NVM 52 may be low as NVM element 52 is in a conductive or low impedance memory state. Here, if NVM element 52 comprises a CES element, a capacitance of NVM 52 may increase or decrease in response to a quantum mechanical physical transformation to place NVM element 52 in different memory states as discussed above, and in the absence of a film connecting terminals of NVM 52.

As NVM element 52 is placed in an insulative or high impedance state (e.g., in a write operation with application of V_(reset) and I_(reset)), current may continue to flow from a bitline BL1 to NVM element 52 even following a transition to an insulative or high impedance memory state. While a resistance of NVM 52 may not permit additional current to flow between terminals of NVM element 52, charge from current flowing from a bitline to NVM element 52 may be stored in a capacitance of NVM element 52. As the bitline is disconnect from NVM element 52, charge stored in the capacitance of NVM 52 may dissipate through the resistance of NVM 52.

FIGS. 7A and 7B are schematic diagrams of a bitcell according to particular embodiments. Here, NVM elements 72 and 74 may comprise distinct CeRAM devices and are coupled between complementary bitlines BL and NBL capable of providing output voltages across terminals of the CeRAM devices during write operations (e.g., 0.6 V to place the CeRAM devices in an insulative or high impedance memory state and 1.2 V to place the CeRAM devices in a conductive or low impedance memory state). In this context, “complementary” bitlines transmit signals that are distinguishable yet are generated in combination to provide a particular result. In the particular implementation of FIG. 7A, during a read operation, a voltage of signal REN may drop (e.g., drop to 0.0 V) to close FETs M24 and M25 (formed as PFETs in the particular implementation of FIG. 7A) to connect terminals of NVMs 72 and 74 between read voltage supply RVDD and a reference node 73 (e.g., a node connected to a ground). Read voltage supply RVDD may provide a voltage signal maintained at 0.4 V, for example. In the particular implementation of FIG. 7A, during a write operation, a voltage of signal REN may be raised (e.g., raised to an output voltage of read voltage supply RVDD) to open FETs M24 and M25, disconnecting read voltage supply RVDD from nodes 11 and 12.

Like the particular implementation of FIG. 5E, bitline BL may be connected to NVM 72 through transmission gate T1 and bitline NBL may be connected to NVM 74 through transmission gate T2. Transmission gates T1 and T2 each comprise an NFET and a PFET. NFETs of transmission gates T1 and T2 in a closed state may conduct low currents between nodes 1 and 11, and between nodes 12 and 13 during write operations while PFETs of transmission gates T1 and T2 in a closed state may conduct higher currents (e.g., I_(reset)) during write operations. In a particular implementation, a voltage of signal PGM may be raised (e.g., raised to VDD) during read operations to open the PFET portions of transmission gates T1 and T2, and lowered (e.g., lowered to 0.0 V) during write operations to close the PFET portions of transmission gates T1 and T2. Likewise, in a particular implementation a voltage of wordline signal WL may be raised (e.g., raised to VDD) during read operations to close NFET portions of transmission gates T1 and T2, and lowered during write operations to open NFET portions of transmission gates T1 and T2. In alternative implementations shown above in FIGS. 7C and 7E, PFET portions of transmission gates T1 and T2 may be omitted and a driver for signal WL may “boost” a voltage of WL provided to gates of remaining NFET portions to enable sufficient current to pass between nodes 1 and 11, and between nodes 12 and 13 during write operations. Likewise, as shown in the particular implementation of FIG. 7D, NFET portions of transmission gates T1 and T2 may be omitted.

In the particular implementation of FIG. 7B, NVM elements 72 and 74 are connected to read voltage source RVDD at first terminals and connected FETs M26 and M27 at second terminals. During a read operation, FETs M26 and M27 may close in response to a raised read enable signal REN to connect NVM elements 72 and 74 to a reference node. During read operations, an output signal from read voltage source RVDD may be maintained at 0.4 V, for example. During write operations, the output signal from read voltage source RVDD may be maintained at 0.0 V, for example.

In the particular embodiments discussed above in FIGS. 7A and 7B, complementary bitlines may place NVM elements 72 and 74 in complementary memory states in write operations. For example, a first particular write operation may place NVM 72 in a conductive of low impedance memory state and place NVM 74 in a reset memory state while a second particular write operation may place NVM 72 in a reset memory state and place NVM 74 in an insulative or high impedance memory state. Here, according to an embodiment, the particular first and second write operations may be used to have the memory states of NVM 72 and 74 represent a particular value of two possible values (e.g., a “1” or a “0”). For example, a “0” may be represented by NVM 72 being in an insulative or high impedance memory state while NVM 74 is in a conductive or low impedance memory state, and a “1” may be represented by NVM 72 being in an insulative or high impedance memory state while NVM 74 is in a conductive or low impedance memory state.

In an alternative embodiment, memory states of NVM 72 and 74 together may represent a particular value of four possible values (e.g., “00,” “01,” “10” or “11”). In an implementation, four particular write operations may be used for placing NVMs 72 and 74 in particular memory states to represent a particular value from four possible values. For example, a first write operation may place NVM 72 and NVM 74 in an insulative or high impedance memory state, a second write operation may place NVM 72 in an insulative or high impedance memory state and place NVM 74 in a conductive or low impedance memory state, a third write operation may place NVM 72 in an insulative or high impedance memory state and place NVM 74 in a conductive or low impedance memory state, and a fourth write operation may place NVM 72 and NVM 74 in a conductive or low impedance memory state.

It should be understood that the particular embodiments shown in FIGS. 7A and 7B are merely examples, and that other implementations may have different features without deviating from claimed subject matter. For example, the particular implementation of FIG. 7A may be altered by replacing transmission gates T1 and T2 with NFETs or PFETs M71 and M72 as shown in FIGS. 7C and 7D. Likewise, the particular implementation of FIG. 7B may be altered by replacing transmission gates T1 and T2 with NFETs M71 and M72.

FIGS. 8A, 8B and 8C are schematic diagrams of bitcell circuits comprising NVM elements 82 and 84 which may be formed as CeRAM elements. In one aspect, a first terminal of a first non-volatile memory element (e.g., a first CeRAM element) may be connected to a first terminal of a first conducting element responsive to a first voltage at a first terminal of a second non-volatile memory element (e.g., a second CeRAM element). Similarly, a first terminal of the second non-volatile memory element may be connected to a first terminal of a second conducting element responsive to a second voltage at the first terminal of the first non-volatile memory element.

According to an embodiment, NVM elements 82 and 84 may be placed in complementary memory states to represent a particular value, condition or state, etc. out of two different values, conditions or states. For example, to represent a first value, condition or state (e.g., a “0”), NVM element 82 may be placed in a conductive or low impedance memory state while NVM element 84 may be placed in an insulative or high impedance memory state. Likewise, to represent a second value, condition or state (e.g., a “1”), NVM element 82 may be placed in an insulative or high impedance memory state while NVM element 84 may be placed in a conductive or low impedance memory state. In a particular implementation, a first write operation may apply a first programming signal to NVM element 82 to place NVM element 82 in a conductive or low impedance memory state and apply a second programming signal to NVM element 84 to place NVM element 84 in an insulative or high impedance memory state. For example, the first programming signal may comprise a particular write voltage (e.g., V_(set)) and a particular write current (I_(set)), and the second programming signal may comprise a complementary write voltage (e.g., V_(reset)) and a complementary write current (I_(reset)). Similarly, a second write operation may apply a first programming signal to NVM element 82 to place NVM element 82 in an insulative or high impedance memory state and apply a second programming signal to NVM element 84 to place NVM element 84 in a conductive or low impedance memory state. For example, the first programming signal may comprise a particular write voltage (e.g., V_(reset)) and a particular write current (I_(reset)), and the second programming signal may comprise a complementary write voltage (e.g., V_(set)) and a complementary write current (I_(set)). Detection of the individual memory states of NVM element 82 and NVM element 84 in a read operation may then be mapped to a “0” or a “1.”

In one particular implementation where NVM element 82 and NVM element 84 comprise CeRAM devices, in placing NVM 82 or NVM 84 in a conductive or low impedance memory state, or an insulative or high impedance memory state in either of the aforementioned first and second write operations, a magnitude of a particular write voltage of a first programming signal to place an NVM element in a conductive or low impedance memory state (e.g., V_(set)) is greater than a magnitude of a particular write voltage of a second programming signal to place the NVM element in an insulative or high impedance memory state (e.g., V_(reset)). Furthermore, in placing NVM 82 or NVM 84 in a conductive or low impedance memory state, or an insulative or high impedance memory state in either of the aforementioned first and second write operations, a magnitude of a particular write current of a first programming signal to place an NVM element in a conductive or low impedance memory state (e.g., I_(set)) may be less than a magnitude of a particular write current of a second programming signal to place the NVM element in an insulative or low impedance memory state (e.g., I_(reset)).

Particular implementations of FIGS. 8A and 8B position NVM elements 82 and 84 to be connected to a voltage supply VVDD at first terminals and connected to complementary bitlines BL and NBL during read and write operations at second terminals at nodes 8 and 9. Second terminals of NVM elements 82 and 84 may be further connected to a reference node 83 through cross-coupled FETs M21 and M22. Here, cross-coupling FETs M21 and M22 by connecting node 8 to a gate terminal of FET M22 to provide a first voltage signal and connecting node 9 to a gate terminal of FET M21 to provide a second voltage signal may limit drawing current from a single NVM element (e.g., NVM element 82 or 84) during read operations.

In the particular implementations of FIGS. 8A and 8B, voltage supply VVDD may be switchable between two different voltages for read and write operations. For example, voltage supply VVDD for implementations according to FIG. 8A or 8B may maintain an output signal at 0.4 V during read operations. In the particular implementation of FIG. 8A, voltage supply VVDD may maintain an output signal at 0.0 V during write operations. In the particular implementation of FIG. 8B, voltage supply VVDD may maintain an output signal at 1.2 V during write operations.

The particular implementations of FIGS. 8A and 8B further comprise FETs to optionally place a bitcell in a retention mode (e.g., to reduce power consumption) in response to a lowering of a voltage on signal EN applied to gate terminals. Here, FET M18 may connect an output signal of voltage supply VVDD to terminals of NVM elements 82 and 84 during read and write operations, and disconnect output signal of voltage supply VVDD while neither a read or write operation is occurring. Similarly, FET M23 may connect FETs M21 and M22 to reference node 83 during read and write operations, and disconnect FETs M21 and M22 from reference node 83 while neither a read or write operation is occurring.

In the particular implementations, of FIGS. 8A, 8B and 8C, bitlines BL and NBL are connected to terminals of NVM elements 82 and 84 by FETs M19 and M20 in response to a raised voltage on wordline signal WL during read and write operations. During write operations, voltages on bitlines BL and NBL may drive voltages across NVM elements 82 and 84 sufficiently high to place NVM elements 82 and 84 in complementary memory states (e.g., 0.6 V and 1.2 V). While FIGS. 8A, 8B and 8C show that terminals of NVM elements 82 and 84 are connected to bitlines BL and NBL through single NFET devices, a voltage on wordline signal WL may be “boosted” to accommodate larger currents during write operations as discussed above. In an alternative implementation, FETs M19 and M20 may be replaced with transmission gates comprising an NFET (to conduct smaller currents during read operations) and a PFET (to conduct larger currents during write operations).

In the particular implementation of FIG. 8C, FETs M21 and M22 may be formed as PFETs. Also, a read voltage supply RVDD may be connected to FETs M21 and M22 during read operations by closing PFET M18 responsive to a lowered voltage of read enable signal REN to provide an output signal maintained at 0.4 V. One of ordinary skill in the art should recognize that the particular implementations of FIGS. 8A, 8B and 8C are merely example implementations, and that aspects of these implementations may be modified without deviating from claimed subject matter. For example, as shown in FIG. 8D, the particular implementation of FIG. 8C may be modified by replacing NFETs of FETs M19 and M20 with PFETs. Also, as shown in FIG. 8E, the implementation of FIG. 8D may be further modified by removing FET M18 such that NVM elements 82 and 84 remain connected to read supply voltage RVDD. Alternatively, as shown in FIG. 8F, the implementation of FIG. 8D may be modified by replacing FET M18 in a pull-up position with FET M24 in a pull-down position to connect NVM elements 82 and 84 to reference node 83 in a read operations. Also, as shown in the particular implementation of FIG. 8G, the implementation of FIG. 8A may be modified by removal of FET M24 shown in FIG. 8G.

References throughout this specification to one implementation, an implementation, one embodiment, an embodiment and/or the like means that a particular feature, structure, and/or characteristic described in connection with a particular implementation and/or embodiment is included in at least one implementation and/or embodiment of claimed subject matter. Thus, appearances of such phrases, for example, in various places throughout this specification are not necessarily intended to refer to the same implementation or to any one particular implementation described. Furthermore, it is to be understood that particular features, structures, and/or characteristics described are capable of being combined in various ways in one or more implementations and, therefore, are within intended claim scope, for example. In general, of course, these and other issues vary with context. Therefore, particular context of description and/or usage provides helpful guidance regarding inferences to be drawn.

While there has been illustrated and described what are presently considered to be example features, it will be understood by those skilled in the art that various other modifications may be made, and equivalents may be substituted, without departing from claimed subject matter. Additionally, many modifications may be made to adapt a particular situation to the teachings of claimed subject matter without departing from the central concept described herein. Therefore, it is intended that claimed subject matter not be limited to the particular examples disclosed, but that such claimed subject matter may also include all aspects falling within the scope of the appended claims, and equivalents thereof. 

1. A device comprising: a voltage supply to generate a read supply voltage; a first CES element; a first conducting element to connect a bitline to a terminal of the first CES element in response to a wordline voltage signal during a read operation and a write operation, the first conducting element to permit a voltage and a current between the bitline and the terminal of the first CES element during the read operation and to permit an increased voltage and current between the bitline and the terminal of the first CES element during the write operation; and a second conducting element to connect the first CES element between the voltage supply and a reference node during the read operation and to isolate the first CES element from the voltage supply or the reference node in the write operation.
 2. The device of claim 1, wherein the first conducting element comprises a transistor to receive a the wordline voltage at a gate terminal, and wherein the wordline voltage is boosted during said write operation to allow an increased voltage and current between the bitline and the terminal of the first CES element.
 3. The device of claim 1, wherein the first conducting element comprises an NFET transistor having an NFET gate to receive a first wordline voltage during the read operation, the NFET transistor to receive a boosted wordline voltage during the write operation.
 4. The device of claim 1, wherein the second conducting element is coupled between the voltage supply and the first CES element.
 5. The device of claim 1, wherein the second conducting element is coupled between the first CES element and the reference node.
 6. The device of claim 1, wherein the first conducting element comprises a PFET transistor having a PFET gate to receive a first wordline voltage during the read operation, the PFET transistor to receive a second wordline voltage during the write operation.
 7. The device of claim 1, wherein the reference node is connected to a ground.
 8. The device of claim 1, wherein the device further comprises: a second CES element; and a third conducting element to connect a complementary bitline to a terminal of the second CES element in response to the wordline voltage signal during the read operation and the write operation, the third conducting element to permit a voltage and a current between the complementary bitline and the terminal of the second CES element during the read operation and to permit an increased voltage and current between the complementary bitline and the terminal of the second CES element during the write operation, wherein the second conducting element is further to connect the second CES element between the voltage supply and the reference node during the read operation, and isolate the second CES element from the voltage supply or the reference node during the write operation.
 9. The device of claim 8, wherein the third conducting element comprises a first transmission gate to permit a first current level between the complementary bitline and the terminal of the second CES element in response to the wordline signal during the read operation, and to permit a second current level between the complementary bitline and the terminal of the second CES element during the write operation, the second current level being higher than the first current level.
 10. The device of claim 8, wherein the first conducting element comprises a first PFET transistor to connect the voltage source to the first CES element during the read operation and disconnect the voltage source from the first CES element during the write operation, and further comprises a second PFET transistor to connect the voltage source to the second CES element during the read operation and disconnect the voltage source from the second CES element during the write operation.
 11. The device of claim 8, wherein the first conducting element comprises a first NFET transistor to connect the voltage source to the first CES element during the read operation and disconnect the voltage source from the first CES element during the write operation, and further comprises a second NFET transistor to connect the voltage source to the second CES element during the read operation and disconnect the voltage source from the second CES element during the write operation.
 12. The device of claim 8, wherein the first conducting element comprises a first NFET transistor to connect the reference node to the first CES element during the read operation and disconnect the reference node from the first CES element during the write operation, and further comprises a second NFET transistor to connect the reference node to the second CES element during the read operation and disconnect the reference node from the second CES element during the write operation.
 13. The device of claim 8, wherein the first conducting element comprises a first PFET transistor to connect the reference node to the first CES element during the read operation and disconnect the reference node from the first CES element during the write operation, and further comprises a second PFET transistor to connect the reference node to the second CES element during the read operation and disconnect the reference node from the second CES element during the write operation.
 14. The device of claim 1, wherein the first CES element is capable of being placed in at least a conductive or low impedance memory state and a insulative or high impedance memory state, and wherein the first CES element is capable of being placed in the set memory state in a first write operation by application of first current and a first voltage across terminals of the CES element, or a second write operation comprising second voltage and a second current across terminals of the CES element, wherein the second voltage is opposite the first voltage and the second current is opposite the first current.
 15. The device of claim 1, wherein the first conducting element comprises an NFET coupled between the first terminal of the first CES element and the bitline, the NFET to connect the first terminal of the first CES element during the write operation in response to a first wordline signal, and wherein the first conducting element further comprises a PFET coupled between the first terminal of the first CES element and the bitline, the PFET to connect the first terminal of the first CES element to the bitline during the write operation in response to a second wordline signal.
 16. The device of claim 11, wherein the first CES element comprises a CeRAM element.
 17. A method comprising: connecting a bitline to a first terminal of a first non-volatile memory element through a first conducting element in response to a wordline voltage signal while connecting the first non-volatile memory element between a read supply voltage and a reference node during a read operation; connecting the bitline to the first terminal of the first non-volatile memory element through the first conducting element in response to the wordline voltage signal while isolating the first non-volatile memory element from the read supply voltage or the reference node during a first write operation, the first write operation applying a first write voltage and a first write current between the first terminal of the first non-volatile memory element and a second terminal of the first non-volatile memory element to place the first non-volatile memory element in a first memory state; connecting the bitline to the first terminal of the first non-volatile memory element through the first conducting element in response to the wordline voltage signal while isolating the first non-volatile memory element from the read supply voltage or the reference node during a second write operation, the second write operation applying a second write voltage and a second write current between the first terminal of the first non-volatile memory element and the second terminal of the first non-volatile memory element to place the first non-volatile memory element in a second memory state; wherein a magnitude of the first write voltage is greater than a magnitude of the second write voltage, and a magnitude of the first write current is less than a magnitude of the second write current.
 18. The method of claim 17, and further comprising: applying a third write voltage and a third current between terminals of the first non-volatile memory element to place the first non-volatile memory element in the first memory state, the third write voltage being opposite the first write voltage and the third write current being opposite the first write current.
 19. The method of claim 18, and further comprising: applying a fourth write voltage and a fourth current between terminals of the first non-volatile memory element to place the first non-volatile memory element in the second memory state, the fourth write voltage being opposite the second write voltage and the fourth write current being opposite the second write current.
 20. The method of claim 17, and further comprising: connecting a complementary bitline to a first terminal of a second non-volatile memory element through a second conducting element in response to a wordline voltage signal while connecting the second non-volatile memory element between the read supply voltage and the reference node during the read operation; connecting the complementary bitline to the first terminal of the second non-volatile memory element through the second conducting element in response to the wordline voltage signal while isolating the second memory element from the read supply voltage or the reference node during the first write operation, the first write operation further applying a third write voltage and a third write current between the first terminal of the second non-volatile memory element and a second terminal of the second non-volatile memory element to place the second non-volatile memory element in the first memory state; and connecting the complementary bitline to the first terminal of the second non-volatile memory element through the second conducting element in response to the wordline voltage signal while isolating the second non-volatile memory element from the read supply voltage or the reference node during a second write operation, the second write operation applying a fourth write voltage and a fourth write current between the first terminal of the second non-volatile memory element and the second terminal of the second non-volatile memory element to place the first non-volatile memory element in the second memory state; wherein a magnitude of the third write voltage is greater than a magnitude of the fourth write voltage, and a magnitude of the third write current is less than a magnitude of the fourth write current.
 21. The method of claim 17, wherein the first non-volatile memory device comprises a CES device.
 22. The method of claim 17, wherein the first non-volatile memory device comprises a CeRAM device.
 23. A device comprising: a first CES element; a second CES element; a first conducting element having a first terminal connected to a first terminal of the first CES element; a second conducting element having a first terminal connected to a first terminal of the second CES element a third conducting element to connect the first terminal of the first CES element to a bitline responsive to a wordline voltage; and a fourth conducting element to connect the first terminal of the second CES element to an complementary bitline responsive to the wordline voltage, wherein the first conducting element comprises a second terminal connected to a second terminal of the second conducting element, wherein the first conducting element is further to connect the first terminal of the first CES element to the second terminal of the second conducting element responsive to a first voltage at the first terminal of the second CES element, and wherein the second conducting element is further to connect the first terminal of the second CES element to the second terminal of the first conducting element responsive to a second voltage at the first terminal of the first CES element.
 24. The device of claim 23, the device further comprising a voltage source to provide a first output voltage during a read operation, wherein the first conducting element is further to connect the first CES element between the voltage source and a reference node responsive to the first voltage, and wherein the second conducting element is further to connect the second CES element between the voltage source and the reference node responsive to the second voltage.
 25. The device of claim 24, wherein the voltage source is connected to a second terminal of the first CES and a second terminal of the second CES element during the read operation and during the write operation, and wherein application of the first output voltage to the second terminal of the first CES element limits a voltage between the first and second terminals of the first CES element and a voltage between the first and second terminals of the second CES element to maintain a conductive or low impedance memory state of the first and second non-volatile memory elements during the read operation.
 26. The device of claim 23, and further comprising a fifth conducting element to connect the first and second CES elements to the voltage supply during the read, and disconnect the first and second CES elements from the voltage supply while the device is in a retention mode and write operation.
 27. The device of claim 23, and further comprising a fifth conducting element to connect the first and second conducting elements to a reference node during the read, and disconnect the first and second conducting elements from the reference node while the device is in a retention mode or write operation.
 28. The device of claim 23, wherein the voltage supply is further to provide a second output voltage during a write operation.
 29. The device of claim 23, and further comprising a third conducting element to connect the first terminal of the first CES element to a bitline responsive to a wordline voltage, and a fourth conducting element to connect the first terminal of the second CES element to an complementary bitline responsive to the wordline voltage.
 30. The device of claim 23, wherein the first conducting element is coupled between the first CES element and a voltage source to connect the first terminal of the first CES element to the voltage source in response to the first voltage, and wherein the second conducting element is coupled between the second CES element and the voltage source to connect the first terminal of the second CES element to the voltage source in response to the second voltage.
 31. The device of claim 23, wherein the first CES element comprises a first CeRAM element, and wherein the second CES element comprises a second CeRAM element.
 32. A method comprising: connecting a first terminal of a first non-volatile memory element to a first terminal of a first conducting element responsive to a first voltage at a first terminal of a second non-volatile memory element; and connecting the first terminal of the second non-volatile memory element to a first terminal of a second conducting element responsive to a second voltage at the first terminal of the first non-volatile memory element; performing a first write operation to place the first non-volatile memory element in a first memory state and place the second non-volatile memory element in a second memory state, the first write operation comprising applying at least a first programming signal between the first and second terminals of the first non-volatile memory element to place the first non-volatile memory element in the first memory state, the first programming signal comprising a first write voltage and a first write current; and performing a second write operation to place the first non-volatile memory element in the second memory state and place the second non-volatile memory element in the first memory state, the second write operation comprising applying at least a second programming signal between the first and second terminals of the first non-volatile memory element to place the first non-volatile memory element in the second memory state, wherein a magnitude of the first write voltage is greater than a magnitude of the second write voltage, and a magnitude of the first write current is less than a magnitude of the second write current.
 33. The method of claim 32, wherein the first memory state comprises a conductive or low impedance memory state and the second memory state comprises an insulative or high impedance memory state.
 34. The method of claim 32, wherein the first and second non-volatile memory elements comprise first and second CES elements.
 35. The method of claim 32, wherein the first and second non-volatile memory elements comprise first and second CeRAM elements. 